Product name title=UM10462 Chapter title=LPC11U1x USART Modification date=3/16/2011 Major revision=0 Minor revision=3 (USART)
#include <LPC11Uxx.h>
Veřejné atributy | |
union { | |
__IO uint32_t DLL | |
__O uint32_t THR | |
__I uint32_t RBR | |
}; | |
union { | |
__IO uint32_t IER | |
__IO uint32_t DLM | |
}; | |
union { | |
__O uint32_t FCR | |
__I uint32_t IIR | |
}; | |
__IO uint32_t | LCR |
__IO uint32_t | MCR |
__I uint32_t | LSR |
__I uint32_t | MSR |
__IO uint32_t | SCR |
__IO uint32_t | ACR |
__IO uint32_t | ICR |
__IO uint32_t | FDR |
__IO uint32_t | OSR |
__IO uint32_t | TER |
__I uint32_t | RESERVED0 [3] |
__IO uint32_t | HDEN |
__I uint32_t | RESERVED1 |
__IO uint32_t | SCICTRL |
__IO uint32_t | RS485CTRL |
__IO uint32_t | RS485ADRMATCH |
__IO uint32_t | RS485DLY |
__IO uint32_t | SYNCCTRL |
union { ... } |
< (@ 0x40008000) USART Structure
__IO uint32_t LPC_USART_Type::ACR |
(@ 0x40008020) Auto-baud Control Register. Contains controls for the auto-baud feature.
__IO uint32_t LPC_USART_Type::DLL |
(@ 0x40008000) Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1)
__IO uint32_t LPC_USART_Type::DLM |
(@ 0x40008004) Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1)
__O uint32_t LPC_USART_Type::FCR |
(@ 0x40008008) FIFO Control Register. Controls USART FIFO usage and modes.
__IO uint32_t LPC_USART_Type::FDR |
(@ 0x40008028) Fractional Divider Register. Generates a clock input for the baud rate divider.
__IO uint32_t LPC_USART_Type::HDEN |
(@ 0x40008040) Half duplex enable register.
__IO uint32_t LPC_USART_Type::ICR |
(@ 0x40008024) IrDA Control Register. Enables and configures the IrDA (remote control) mode.
__IO uint32_t LPC_USART_Type::IER |
(@ 0x40008004) Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential USART interrupts. (DLAB=0)
__I uint32_t LPC_USART_Type::IIR |
(@ 0x40008008) Interrupt ID Register. Identifies which interrupt(s) are pending.
__IO uint32_t LPC_USART_Type::LCR |
(@ 0x4000800C) Line Control Register. Contains controls for frame formatting and break generation.
__I uint32_t LPC_USART_Type::LSR |
(@ 0x40008014) Line Status Register. Contains flags for transmit and receive status, including line errors.
__IO uint32_t LPC_USART_Type::MCR |
(@ 0x40008010) Modem Control Register.
__I uint32_t LPC_USART_Type::MSR |
(@ 0x40008018) Modem Status Register.
__IO uint32_t LPC_USART_Type::OSR |
(@ 0x4000802C) Oversampling Register. Controls the degree of oversampling during each bit time.
__I uint32_t LPC_USART_Type::RBR |
(@ 0x40008000) Receiver Buffer Register. Contains the next received character to be read. (DLAB=0)
__IO uint32_t LPC_USART_Type::RS485ADRMATCH |
(@ 0x40008050) RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode.
__IO uint32_t LPC_USART_Type::RS485CTRL |
(@ 0x4000804C) RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes.
__IO uint32_t LPC_USART_Type::RS485DLY |
(@ 0x40008054) RS-485/EIA-485 direction control delay.
__IO uint32_t LPC_USART_Type::SCICTRL |
(@ 0x40008048) Smart Card Interface Control register. Enables and configures the Smart Card Interface feature.
__IO uint32_t LPC_USART_Type::SCR |
(@ 0x4000801C) Scratch Pad Register. Eight-bit temporary storage for software.
__IO uint32_t LPC_USART_Type::TER |
(@ 0x40008030) Transmit Enable Register. Turns off USART transmitter for use with software flow control.
__O uint32_t LPC_USART_Type::THR |
(@ 0x40008000) Transmit Holding Register. The next character to be transmitted is written here. (DLAB=0)